Semiconductor memories have undergone intensive research and development in recent years to develop increasingly efficient, faster and less expensive memories for use with microprocessors. The present invention achieves these objectives, when compared with a multitude of prior art memory devices, by using silicon-on-sapphire (SOS) technology.
Basically, logic states in SOS transistors may be altered by ionizing radiation. In the past, it has been observed that bombardment of a silicon-on-sapphire (SOS) N-channel MOS transistor with ionizing radiation gives rise to a "back-channel" leakage current I.sub.l. This current flows between drain and source terminals in the silicon adjacent to the silicon-sapphire interface. Formation of the back channel has been previously attributed to radiation-induced positive charge buildup in the sapphire (Al.sub.2 O.sub.3) substrate near this interface. The increase in I.sub.l with ionizing dose can be as large as three to four orders of magnitude after a dose of 10.sup.3 to 10.sup.5 rads (Si). This increase will be observed if the device is irradiated with a typical value of drain-to-source voltage (V.sub.ds) applied, such as 10 V. The magnitude of the applied gate bias (V.sub.gs) during irradiation appears to be relatively unimportant in terms of affecting leakage current production.